NXP Semiconductors /LPC43xx /USB1 /ENDPTSETUPSTAT

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Interpret as ENDPTSETUPSTAT

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (ENDPTSETUPSTAT0)ENDPTSETUPSTAT0 0 (ENDPTSETUPSTAT1)ENDPTSETUPSTAT1 0 (ENDPTSETUPSTAT2)ENDPTSETUPSTAT2 0 (ENDPTSETUPSTAT3)ENDPTSETUPSTAT3 0RESERVED

Description

Endpoint setup status

Fields

ENDPTSETUPSTAT0

Setup endpoint status for logical endpoints. For every setup transaction that is received, a corresponding bit in this register is set to one. Software must clear or acknowledge the setup transfer by writing a one to a respective bit after it has read the setup data from Queue head. The response to a setup packet as in the order of operations and total response time is crucial to limit bus time outs while the setup lockout mechanism is engaged.

ENDPTSETUPSTAT1

Setup endpoint status for logical endpoints. For every setup transaction that is received, a corresponding bit in this register is set to one. Software must clear or acknowledge the setup transfer by writing a one to a respective bit after it has read the setup data from Queue head. The response to a setup packet as in the order of operations and total response time is crucial to limit bus time outs while the setup lockout mechanism is engaged.

ENDPTSETUPSTAT2

Setup endpoint status for logical endpoints. For every setup transaction that is received, a corresponding bit in this register is set to one. Software must clear or acknowledge the setup transfer by writing a one to a respective bit after it has read the setup data from Queue head. The response to a setup packet as in the order of operations and total response time is crucial to limit bus time outs while the setup lockout mechanism is engaged.

ENDPTSETUPSTAT3

Setup endpoint status for logical endpoints. For every setup transaction that is received, a corresponding bit in this register is set to one. Software must clear or acknowledge the setup transfer by writing a one to a respective bit after it has read the setup data from Queue head. The response to a setup packet as in the order of operations and total response time is crucial to limit bus time outs while the setup lockout mechanism is engaged.

RESERVED

Reserved

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